I said said:
Samuel Clemens (Mark Twain) suppsedly had once stated something along the lines of "it ain't what you don't know that hurts ya, its what you know that just ain't so". Unfortunately, that is partially the case in regards to my comments made the other day. Because I had a notion in my head, and because I searched for support in haste and without due care, I made several errors. Let me now correct my faulty statements, and hopefully put this issue to rest. BTW, this is going to be
extremely long, so if you want to just skip all the details, the end result works out to be essentially the same thing as what I earlier wrote, its just that
some of the stuff in between I royally bungled. So for all you impatient types the summary is this:
largest possible address space with the LX is 16M, and hence the same conclusions about module capacities apply. The key word is "possible" as opposed to supported, and this plays a key role in Sherif's observations and last question (I'll cover this aspect last).
First:Wrong Source
The Intel spec sheets for the 440LX chipset are all found
here. The one I quoted from (The LX Design Guide) was the first one I grabbed which I thought would contain the necessary info (which it partially did, yet I, nonetheless, went on to misinterpret it to fit my predetermined conclusion). Had I been more discerning I would have looked at the
PAC data sheet, which is essentially the "everything you ever wanted to know about the 440LX Northbridge but were afraid to ask". Its the kind of thing that guys like George Breeze dream about - full details of pins, signals, registers and bits...From this document, a complete and fully accurate answer can be derived.
Second: My mistakes.
Earlier,
idiot said:
on Pg.24 said:
In this design, the PAC is configured to interface to a “large” memory array. Two copies of the RAS#/CS# signals are provided in this configuration. There is one copy of memory address bits 13 down to 2....
idiot said:
Meaning bits 0 & 1 are for the RAS\ and CAS\ signals, and bits 2-13 are the 12 address lines.
on Pg.45 said:
Fourteen memory address signals allow the PAC to support a wide variety of DIMMs.
Talk about messing things up. The first thing to correct is that there are indeed fourteen memory address signals/lines for the LX chipset (just like Intel wrote).
All fourteen lines are used exclusively for the transmission of memory addresses. This lies in stark contrast to what I was implying earlier (12 address + 1 RAS\ + 1 CAS\), where I interpreted bits 0 & 1 to be the RAS\ & CAS\ control signals. In fact, The RAS\ and CAS\ control signals run on there own unique pins\traces. Furthermore, I really should have picked up on the "RAS#/CS#", where "CS#" is the chip select signal (which is situated on the same pin as the RAS\ ... its just a shared architecture). To say the least, the sentence "Two copies of the RAS#/CS# signals are provided in this configuration" has no emminent connection with the subsequent one which states "There is one copy of memory address bits 13 down to 2....". The last items of interest I draw your attention to (in this part of the story) are the "PAC is configured to interface to a “large” memory array" sentence, and Intel's later use of the word "configuration". Both of these highlights I'll address shortly.
Third: From the PAC data sheet:
The items of interest from this data sheet can be found on:
pg 2 - a block diagram of all the pins in the PAC
pg 14 - host interface address pins A[31:3] connect to the processor address bus
pg.15-20 - DRAM interface description of the pins and signals
pg.84 Start of all the DRAM interface details !
Note: all further page references I make are also from this document.
The LX can support two different configurations:
* Configuration #1 would involve 4 DIMM slots on the motherboard. This is what Intel reffers to when they wrote "PAC is configured to interface to a “large” memory array".
* Configuration #2, which involves 3 DIMM slots on the motherboard, and is reffered to by Intel as a "small memory array". According to the
manual for Sherif's board, it is of the Configuration #2 type.
* Pg.87 & 88 diagram in detail the layout and pin addressing for the two different configs.
Now given that the LX chipset has 14 memory address lines (instead of the erronous statement of 12), you may wonder about the validity of my earlier statement
I said:
Because of the nature of system memory addressing (its multiplexed across the same memory pins; chipset first sends the row address and then sends the column address on the next clock cycle), this means that the largest array of memory that this chipset can address is 2^24 .... = 16,777,216....in otherwords, it only supports 16M addresses....So your looking at 16Mx* DRAM chips.
Well, as it turns out, it is the heart of this statement which lead me to relook at all of this PAC business. Simply, my statement implies symmetry (a 2^12 x 2^12 array; which, of course, is mathematically equivalent to 2^24). However, for operational reasons, this is not the ideal shape for a
large SDRAM array to take. The reason being that SDRAM memory cells (unlike SRAM) require periodic refreshing to ensure the integrity of the bit (literarly) of data that they contain. The refreshing method used accomplishes this task by sweeping throught the rows of cells. However, when refreshing occurs, you can't access memory. To minimize its hit on performance (ie. to make it less obtrusive), it can be performed more quickly by arranging the memory array in such a manner that there are more columns then there are rows, and indeed, this is exactly how the arrays in DRAM chips are configured.
Getting back to the fundamentals of the PAC, the memory addressing plays out like this (details can be found on pg.92):
* The PAC (aka northbridge, aka memory controller) recieves an address (intended for the system memory) from the CPU on the host interface address lines/pins A[26:3].
* The PAC then translates these (by multiplexing; row followed by column) onto the 14 memory address lines MAx(13:0)....(the x in MAx reffers to the fact that there are two identical copies of the 14 address lines: MAA and MAB. Refer to the diagram on pg.88 for detail on to which DIMM socket each commutes, but really, its not that important to the current discussion)
* the
MAXIMUM possible configurable translation for SDRAM (as outlined in Table 15, pg.92) looks like this:
MAx: 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row
A24 A23 A12 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A11 (
14 unique bits)
Col
A24 A23 A12 P A26 A25 A10 A9 A8 A7 A6 A5 A4 A3 (
10 unique bits)
Note: the numbers are supposed to line up but it didn't work out that way. Also note that the P under MAx[10] for the column strobe is simply the bit used for row precharge. Ignore it, cause it has no bearing on the discussion at hand.
Since we have 24 unique bits, we have get 16M possible addresses. The only other thing noteworthy is that it implies that each row is 2^14 = 16,384 (or 16k) cells long i.e. there are 16k columns in each row. Likewise, the column address implies that each column is composed of 2^10 = 1024 (or 1k) cells i.e. there are 1k rows per column.
Admittedly, I find this 1k x 16k arrangement of the array kind of surprising. I didn't think that 16Mx8 DRAM chips (1bit per cell, 16M cells per array, 8 arrays per chip; yeilds a 128Mbit chip) had their arrays in such a configuration. But I say this only because, from what I've read, more modern 32Mx8 (256Mbit) chips typically (I believe) have their 32M arrays arranged as a 4k rows x 8k columns. I would have thought that the older 16Mx8 chips would also have utilized a more compact array.
Nonethesless, the pin counts and related math don't lie. Second, I'm
really, really starting to jut into unfamilar territory. Perhaps there is something that I'm overlooking, (if there is a system's designer in the house please speak up...to bad cas don't come around no more, cause I imagine he'd know....actually, its kind of good thing that he doesn't, cause he would have easily caught my mistakes and probably hung me out to dry....Anyways, on a personal level, getting any further into the nitty gritty of the translation and addressing isn't something I'm probably going to get look into. Suffice it to say I'm comfortable and fairly confident that the superficial mechanics I've outlined are correct.
So the moral of the story Scotty?: "16M address space is all she can do capt'n, she won't go any higher!". Thus, as I outlined the other day, the limitation of a 128MB capacity per physical bank stands to follow.
---------------------
Is that the end of the story? No Dorthy, we still have one last issue to address.
Sherif's Observations
zx said:
First, I tried with a single 256MB dimm. It worked and was recognized as 256MB. I tried putting another 256MB dimm and it worked. The BIOS recognized both as 512MB of memory. I booted and Windows also sees 512MB of memory.....Then I added the 128MB dimm i had. It worked and the BIOS gave 640MB of RAM. Windows booted normally, but it was slow as hell. It seems it was only the display that was slow. When I moved windows it was drawing at a very slow rate. Programs loaded at normal speed.
zx said:
I wonder though why I can't put another 128MB DIMM without everything slowing down...Maybe I should try with a 256MB DIMM.
I believe that the
most probable reason is simply because the LX's signalling was
never designed to accomodate all six of its physical banks stuffed with 128MB. Indeed, quite clearly on (pg. 92), Intel writes "PAC
supports a maximum of 64-Mbit DRAM device". This is consistant with all (but one) other statements and tables contained in the PAC data sheet. Moreover, they specify a maximum support for 8Mx8 DRAM chips (64Mbit chips), such that when all 3 DIMM slots are populated with memory modules that are each composed of two physical banks, you could have a maximum of 384MB of system memory. Sound familar ?
This is precisely the recommendation that, as Time pointed out, motherboards manufacturers place in their manuals, and the Asus P2L97 is no exception. The
ONLY clue to suggest that anything greater then the maxium supported configuration is
possible comes in the address translation table (table 15, page 92), as discussed in the above section.
time said:
Makes me question what I've been told about memory compatibility
In the case of the LX chipset's PAC, it appears that the use of memory configurations greater then that supported is a serendipitous matter. That there are sufficient address lines necessary for such an accomplishment seems to stem from the the PAC also supporting EDO memory. The signalling and addressing in the case of EDO is slightly different then in the case of SDRAM, and it looks like 14 address lines was the magic number to support the capacity of EDO modules of that day gone by.
Now getting back to the issue of why then, when the third module is added, things (as time suggested) get "wacko" is actually probably fairly simple to explain; it all has to do with loading on the mem bus. For a given amount of memory there is a related amount of capacitance (each memory cell consists of a capacitor and transistor) and resistance (you get trace impedence and resistance for each DIMM slot, each module PCB, and in the traces inside the DRAM chips etc etc). Each time you add more memory (increase the memory density), you place an even greater load on the signalling. Eventually, you'll reach a breaking point, and the added load will too much for the signalling to work under the strict timing requirements involved in memory accesses. You can see where this goes considering that the LX is designed to address DRAM chips with 8M addresses, and in Sherif's case, he's trying to add more and more DIMMs whose chips have 16M addresses. Its probably quite an accomplishment that it actually functions well enough that it can past POST, let alone boot into Windows. Simply, with the two 256MB modules already installed, the little PAC is operating well above and beyond the call of duty. In fact, its probably a bloody miracle that it boots with all three.
How can you get that third module to work? You might not be able too, you may have reached the max before signalling gets too distorted. But you could try the following:
- manually reduce the memory timings in the BIOS to most relaxed settings (this will allow the signalling to negotiate the load over a longer period of time, perhaps enough to meet timing requirements)
- try the smaller DIMMs to see if they work instead of the 128MB module
- you could try using registered modules (if supported) - the buffers on registered modules would probably make this "loading" aspect negligible
- try using ECC DIMMs - slowing the signalling by one clock cycle might also negate the effect of the load on the mem bus (probably same effect as setting most relaxed memory timings would have)
- perhaps another module of better quality (better termination, traces etc etc) might be able to work
Other than that, try running memtest86 to check for any module errors
Another possibility might have to do with the MAB and MAA lines (see Pg. 88 ) but, thats something beyond our control.
-------
Earlier,
I said:
collectively, we all weren't too far off
and I stand by that statement. If you read through the thread and take everyone's comments in context, things add up quite nicely. Second, if you've followed along and come this far, I hope you've learned a thing or two. I know I have.
So, now will you shut up? Yes Dorthy, now I'll shut up. In fact, I think I'll never speak of the LX again.
Cheers, CK
