AMDs MOESI cache

[Cliptin]

This may be old news for some.
Apparently with AMDs MOESI cache coherency protocol, processors in a multi-processor system can read from each others cache. Intel chipsets have a design choice/weakness that makes this either very difficult or impossible.

http://www.lostcircuits.com/motherboard/tyan_s2460/2.shtml

I'm not sure how it workks in practice but it sure sound fast.

As defined by AMD...

 

[Tannin]

No time to read the link right now but,oh gentle CPU gurus, might it be fair of me to say that the desigh philosophies of Intel and AMD seem to be leading them in different directions? Intel toward a very small, very low latency cache, and AMD toward larger and more flexible but higher latency designs?

If so, is it not odd that this seems to be the exact oppposite of their main RAM design philosophies?

 

[Cliptin]

One more thing:

According to this there was data in '95 that:
Our results show that for parallel applications, clustering via shared caches provides an effective mechanism for increasing total number of processors in a system, without increasing the number of invalidations. Combining these results with the cost estimates for shared cluster cache implementations leads to two conclusions: 1) For a four cluster multiprocessor with single chip clusters, two processors per cluster with a smaller cache provides higher performance and better cost/performance than a single processor with a larger cache and 2) this four cluster configuration can be scaled linearly in performance by adding processors to each cluster using MCM [multichip module] packaging techniques.

 

[cquinn]

I am not even a CPU neophyte, but it has always seemed to me that
AMD and Intel were travelling down different roads to the same destination.

Now that Intel is trying to move further away from x86, while AMD is
trying to extend it, do they seem to have diverged.
To me, it seems less like they are choosing opposite directions, than
they are choosing different races to run. AMD is trying to build
rally vehicles, while Intel is moving into racing yachts.

I would think AMDs design is not so much about increasing latency
on the CPU, as it is trying to create more balance by reducing
bottlenecks elsewhere in the system.

Excuse my rambling...

 

[Cliptin]

I get the impression that Intel is solving their problems these days by the brute force method. Now I like a big hammer as well as the next guy but AMDs finesse approach really appeals to me.