Barton, SOI... Am I missing something?

[HellDiver]

Thanks to Coug posting the news on the frontpage I dropped by AMD's website to steal a glance at their latest roadmap.

Aside from leaving me dumbfounded as usual in regards to CHammer/Athlon positioning (WTF is the plan?!?), there was something else that cought my eye. Did anyone notice that the magic abbreviation "SOI" disappeared from Barton's nice pink/violet rectangle? I mean, when it's there - it's there, every single Hammer on the chart has SOI engraved on it (so to speak), but Barton, the one that was supposed to pilot SOI for AMD...

Hmmm... :roll:

 

[HellDiver]

As an afterthought oops: for your convenience : the roadmap...

 

[CougTek]

I dunno what it means HD. Maybe I should think about buying a crystal ball someday for cases like this one.

Do you think their PR bullshitters...Errr, marketing people, would answer if I would send them an e-mail and present myself as a hardware site editor (actually, just semi-co-webmaster of the front page, but they don't have to know that)?

 

[Buck]

I dunno what it means HD. Maybe I should think about buying a crystal ball someday for cases like this one.

Do you think their PR bullshitters...Errr, marketing people, would answer if I would send them an e-mail and present myself as a hardware site editor (actually, just semi-co-webmaster of the front page, but they don't have to know that)?

Give it a try. Tell them that your interest is as an editor and also because you have several resellers around the world asking the same question.

 

[Handruin]

I'd say give it a shot, maybe they'll bite.

 

[CougTek]

That was supposed to be a joke, but apparently, you guys really want me to try? How the hell does an editor is supposed to sound? (browsing old e-mails from Eugene and Davin) I'll try, but don't expect anything.

I'll send the message tomorow morning. It wouldn't be serious to send a formal message at the early hours of the morning...

 

[GIANT]

. .
I recall that a few "decent" graphical CPU roadmaps -- basically, well-illustrated timelines -- used to be available back in the days of Pentium II and Pentium II Xeon technologies. But, I haven't seen anything like those earlier Roadmaps in a while.

I would guess it's because processor product lines have gotten so friggin' complex in recent years that nobody wants to even attempt such a graphic. But, those earlier charts were quite good at showing the evolutions of Katmai, Coppermine, and other technologies as it also showed clockspeed rampings over the calendar quarters.


. .

 

[CougTek]

I don't see who to contact. None of these seems to be appropriate.

Two or three years ago, there was an e-mail provided with each press release at AMD, but it seems that it's no longer the case.

 

[Buck]

You could write something to the effect of:

Greetings:

As a representative of resellers from Australia, Canada, and the United States, and as Editor of StorageForum.net, we are concerned about a suspected change in AMD’s roadmap. In reference, the roadmap here:

< http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_608,00.html>

schedules the new SOI technology to debut with Clawhammer. However, it was once discussed that Barton would introduce this technology. Therefore, our concern is that AMD has pushed the release date of this technology, implicating that there are possible issues. An update or clarification regarding AMD’s next step with SOI would be greatly appreciated, and in advance, thank you for your time.

Regards,

 

[Pradeep]

It seems instead of giving us SOI in Barton, they have decided to up the cache to 512KB. Then intro SOI on the Clawhammers. The question is whether with 2 processors running at the same clock speed, one normal, one SOI, does SOI provide a performance increase in this case? I would imagine it is more an aid to improving clock speeds in the future. I'm happy with a 512KB cache model which should provide a 5-10% boost on most things. Say that is on an 1800 MHz model. Imagining for a minute that performance increases linearly with clock speed (it doesn't) then 10% would be a nearly 200 MHz increase of effective speed. That's 2 or 3 speed steppings.

 

[HellDiver]

You could write something to the effect of:
However, it was once discussed that Barton would introduce this technology.

Actually, make that "stated by AMD" or "announced", not discussed :

...and announced not that long ago, BTW, the slide dates back to Nov 8, 2001 (as far as I can decypher ). I'm also somewhat sure there were even newer mentions by AMD of SOI usage on Barton.

Yeah, a crystal ball would fit the situation nicely...

 

[CougTek]

Thanks Buck for the suggestion. But no matter how good my letter would be, I don't know where to send it. There's apparently no one officially in charge of the marketing at AMD (there is, of course, but I don't see his/her e-mail address).

Who should I contact in that list? My pick would be the sales offices, but they only have phone numbers and no e-mail addresses. Forget contacting them by phone, I speak English like a five years old kid (except for the voice).

 

[Mercutio]

Your English probably sounds like my German.

You might be amused by the essays of David Sedaris on the subject of become an expatriot in Paris, particularly his digressions on the French-language gender of objects in his life. The literal translations of his attempts at French are bad enough to make native English-speakers die laughing.

 

[Buck]

HD,

Thanks for that correction, your suggestions would work perfectly. I was not sure if there was an official post or not, so the word "discussed" seemed like a compromise.

 

[CougTek]

Your English probably sounds like my German.

You mean like Rammstein? Err, perhaps.

I don't think an e-mail will be necessary. As writen in this news at X-bit Labs :

In other words, AMD decided to simply change the Barton’s specifications. Although this core will not be produced with SOI technology, it will boast a twice as big L2 cache than that of Thoroughbred processor: 512KB. It means that Barton is none other but the same Thoroughbred but with larger cache-memory.

 

[LiamC]

Why change the spec for Barton? I believe that AthlonXP is at its frequency limit without a major relayout/process breakthrough. 130nm isn't going to give AMD the big speed gains that Intel achieved with the move to 130nm. In fact the big speed gains came becasue of the use of copper interconnects rather than aluminium - AMD moved to copper for 180nm, while Intel didn't until 130nm.

Intel has also hinted that they will be at 3GHz by year end + 133MHz QDR FSB.

For the current AthlonXP to compete, they'd have to get it to around 2.3~2.4GHz - making a lot of assumptions about the scaling being OK etc. IMHO, not going to happen, and that doesn't take into account the kick the P4 will get from a faster FSB.

But an increase in cache might get them an apparent speed grade or two, maybe even a stretch to three with bigger TLB buffers, so AMD would only need to get their current architecture to 2.1 ~ 2.2GHz, which might be doable by Q1 next year. This should buy AMD the breathing room to transition to Hammer. The added bonus is that it will allow room for more cache for Duron to allow it to compete with Celeron/4 if Intel aggressively ramp the Celly/4 clock speed - and I read an article today that said they expect to have Celeron 4 in the 2 ~ 2.2GHz range by year end. Next year AMD can drop the Duron line altogether, the current Athlon becomes Duron and Hammer is the mainstram/high-end chip.

0.05 - Aus doesn't have 1¢ or 2¢ pieces anymore

 

[HellDiver]

In other words, AMD decided to simply change the Barton's specifications.

Customer : I'll take the Insight! I love the idea of hybrid gasoline-electric engine running under the hood! How much is it? 8)
Honda rep : Uhmm... Ermm... That $20k, but it comes with a <cough, cough> 3 liter diesel those days... :roll:
Customer : 3 liter diesel?!? But hey, that was the whole idea of calling that particular CRX model "Insight" and not CRX - because it had the efficient and environmentally friendly hybrid drive! I can't believe cancelled the Insight!
Honda rep : No, no, no!!! God forbid! We didn't cancel Insight per se - we simply changed the spec!

IMHO, AMD didn't simply change the spec - rather I believe they hit some problems with transitioning T-Bred to SOI, or perhaps with SOI in general. At the moment, the situation for AMD isn't that hilarious performance-wise at all, and AMD know it far better than I do. One doesn't give up at least a couple of steppings of a core that easily when one's CPUs are already walking the very fine line between still being competetive and not being competetive performance-wise, especially when competing against world's #1 chip giant. Doubling the cache alone won't help that much if your core can't go any faster clock-wise...

(The effort totally drained me, so I think I'll call it a dime's worth... :lol: )

 

[CougTek]

Possible explanation for the removal of SOI for Barton (from X-bit Labs) :

One more fact, drawing our attention: AMD refused to continue cooperation with Motorola Company in terms of new technology development. Now they are going to work with UMC on that. I don’t think they did it because they are building a new fab in Singapore together with UMC, they could still have both partnerships. It is most likely to be the 0.13micron technology developed by AMD and Motorola, which appeared not very good and AMD decided to find another partner in this respect.

And the last thing. According to a new AMD roadmap (see this news story), 0.13micron Barton core has changed. Now it will be made not from SOI substrates (which used to be a direct mention of the joint AMD-Motorola technology) but from regular substrates of the silicon dioxide (UMC technologies do not know to use SOI). Here we can’t help recalling that in the end of Q4 UMC was going to start 0.13micron CPUs for AMD. No wonder that Barton core has been changed: it is most likely to be now oriented for UMC’s production lines. And these production lines seem to be pretty good, we should say, as AMD has increased Barton’s cache recently. I think that UMC has already made some trial Thoroughbred processors. And the outcome may have turned out so good that AMD decided to double the L2 cache size (up to 512KB)

Motorola partnership failure in favor of UMC could be the reason.

 

[Pradeep]

Well that's goodnews for AMD users. The last thing we needed was some very slow technology crawl with Motorola dragging the chain. After all look at what Motorola has done to Apple's CPU performance with the G4? Makes sense that the easier chips to produce could be made at the new fab, whilst the more complex Hammers can be made with SOI at Fab30.

I don't see any big performance disparity between an XP2100 and a P4 2.2 GHz. The P4 2.4GHz may well be faster, the hilarious part is when I laugh at the price of $562. Perhaps AMD is in no panic to release faster speed grades. Afterall, would Intel release a P4 3GHz if it was possible tomorrow? Of course not. It would put out itty bitty speed steps, sucking the consumer dry at every step. This is how it has always been. Also, AMD are doing well in the notebook stakes, where the most profits are to be had. A mobile AthlonXP at 1.5 GHz, now running a 266MHz bus, is faster than the p4-m 1.7GHz.

 

[HellDiver]

Josh Walrath at Penstarsys has a curious writeup up. "An exercise in Forward Thinking" as he calls it, though it has a distinct taste of "The Way I Wish Things Were" to it (at least I surely would like things to be anywhere that optimistic!). Have a lookie.

Without commenting on the article as a whole, I'll just note the last passage :

Can you imagine the worker at Best Buy showing a customer an Athlon XP 64 machine and saying, "This supports 64 bit processing, while that Pentium 4 over there ONLY supports 32 bit..." Where do you think the sale will go in most instances?

This one really cracked me up. If you ask me the situation will rather look as follows :

Joe Schmoe: Well, what do you suggest I should get for my son? He's mostly playing those new expensive games <pained look on his face>, so it better run games real fast!
BB employee : You should definitely get the new Pentium 4 3 GigaHurts system sir! It's a speed demon! Really! Completely unbeatable!
Joe Schmoe: Is it... <pulls a napkin with something scribbled on it out of his pocket, tries to read> Does it... Does it byte "sixty four"? Is it "sixty four" bitten? Can it byte "sixty four" all at once? <blushes, no idea what he's asking about>
BB employee : I beg your pardon?
Joe Schmoe: Well, on telly today I've seen some professor talk about those new computers, he said they can do something with their teeth and number "64"... He said they were really advanced to byte like that!
BB employee : Oh, you mean is it 64 bit, sir?
Joe Schmoe: Right, right! 64 bit! I knew it had something to do with bytemarks! So, is it?
BB employee : Well, no sir, but why would you want to buy a 64 bit clone CPU made somewhere in China for your son anyway? You see, those clone thingies only run at 2 GigaHurts, while this super-hypelined, piper-scalar, NetBlast-architectured, internet-accelerated wonderful Pentium 4 system runs at 3 GigaHurts! It is a whole one GigaHurts faster, and it's an original all-American Intel product! Besides, there are no games that can byte them thingies sixty four at a time right now, and won't be any in the next five years because no one knows how to byte more than he can chew anyway!
Joe Schmoe: But on the telly they said...
BB employee : Aw, c'mon! Haven't you seen the blue men on the same channel yesterday, with the spaceman landing and telling them how fast the latest dual-sidelined, NetBoom-powered, raster-vectorizing Pentium 4 processor is? Well, who'd you rather believe, some senile boffin who can't tell a Pentium processor from a Kenwood food processor, or Intel's blue men? 3 Gigahurts, sir, 3 full GigaHurts! Think about it!!!
Joe Schmoe: Damn, you're right, of course! See, it's my wife, she made me write those damned "bytes" down and told me to ask you about them! Women! I knew I shouldn't have listened to her! <throws the napkin into trash bin> How much is for this hurts-a-lot-faster Pentagon thing then?
BB employee : That'll be just $4999 before-taxes-without-monitor-and-no-Windoze, and you get a top-of-the-line, best-of-breed, anti-static, anti-dynamic, fully textured mouspad with big BEST BUY logo on it for free!!!
Joe Schmoe: Wow! Really? The mouse-thingie is absolutely free? Wrap it up then, this GigaHurts Pentagram progressor is my kind of progressor!!!

 

[Tea]

Excellent thread guys, I'm learning stuff. Keep it up.

But just to throw in a bit of perspective, let's consider that notion of "itty-bitty speed steppings" that Cougtek mentioned - because the truth of the matter is that they are all piss-poor little itty-bitty steppings now.

Just yesterday, I happened to do a quick calculation. I was pondering the relative difference between the old 386SX-25 (which was a slug) and the 386SX-33 (which was not a bad little goer), and wondering why there seemed to be such a big difference between the two. One reason, of course, is that the 25 to 33MHz increase applied to the whole damn system: CPU, mainboard, and RAM as well.

At that point, I wondered how these 7MHz increases to all three would translate to modern hardware, so I fired up Quattro Pro and did some sums. Just taking the raw numbers and applying the same improvement to a modern system was a little tricky, as I needed an example where CPU and RAM and FSB all increased by the same percentage, and these days, of course, all three are completely seperate.

But I found an example that fitted almost exactly:

Take a system running a Thunderbird 1000 A (that's the old Thunderbird, the 200MHz FSB one) with an AMD 750 or KT-133 chipset (i.e., the 200MHz FSB one, not the 'vastly improved' KT-133A), and in it you have some old PC-100 RAM - i.e., you have carried your RAM over from whatever it was you had before the Thunderbird - a P-II or a K6-2 perhaps, and are not actually using the 133MHz RAM ability of the motherboard.

Now, do an upgrade on it. Plug in an Athlon 1333 at 266MHz FSB on a KT-133A main board, and replace your RAM with PC-133.

And that, gentlemen is the almost exact mathematical equivalent of one single speed grade in the old days.

Hell, Tannin and I nearly wet our pants over the improvement that going from a Thunderbird 1100A to a 1200C made. "Wow!" we said, "that's about three speed grades worth!" And indeed it was. 1100A to 1200C made as much or more difference than 800A to 900A to 1000A to 1100A.

But let's be conservative and call the 200 to 266 FSB change the equivalent of a mere two CPU speed grades. That means that one of the old speed grades (386SX-25 to 386SX-33) is the mathematical equivalent of going ... er ... 1000A, 1100A, 1200A, 1300A, plus two for the "A" to "C" transition" - in other words, at least five whole speed grades by modern standards.

Doubtless, one could find a different equivalent in the modern Intel chips to, but I think the point is made: they are all itty-bitty trivial improvements these days.

 

[HellDiver]

Actually, that's an old trick, Tony - such calculations were done many times in the past. One tiny thing you left out : how long did it take for such single speed grade upgrade to appear back then and how long does it take now. IIRC Moore's Law is still pretty much in full bloom.

The "itty-bitty speed steppings" are just a proof that it's getting more and more difficult to keep up with Moore's Law by using old techniques while struggling with an old backwards architecture. In part - this is the reason why I consider x86-64 be harmful per se, be that from AMD or from Intel. Trying to make x86 CPUs run faster is akin to trying to run faster yourself with a pair of concrete blocks on your feet instead of shoes. If the same amount of resources was poured into Alpha in the last decade as was poured into x86, I think Moore would have to admit he was overly pessimistic.

 

[Tea]

How long did it take?

Zero years, zero days, and zero minutes: they were both announced at the same time in January 1989.

But that does not invalidate your point, of course, HD. Moore's Law has proven to be astonishingly accurate.

Perhaps a fairer way to look at the rate of progress back then would be to look at the release dates of the 386DX-25 and 33. Hang on a tic and I'll look them up ....

486DX-25 was released in April 88, the DX-33 in April 89, just one year later. (And the performance relationship of those two chips was, of course, exactly the same.)

Hmm .... The DX-33 was released after the SX-33? Can that be right? I just double-checked my notes buy that is what they say, and Chiplist doesn't give a date at all. I'll have to see if I can dig some confirmation, it seems odd.

Thunderbird 1000 was released in June 2000, Thunderbird 1333 in March 2001. Nine months instead of twelve. But that was an uncommonly fast period of progress, in broad, HD, yes, Moore's Law still holds.

The point I was really getting at is that if the chip makers had behaved the way they do now bak then we would have been inflicted with the 386SX-25, 386SX-26, 386SX-27, and so on, all the way up to SX-33.

In those days, spending money on a single CPU speed step for an upgrade was worth doing. These itty-bitty steppings you get these days aren't worth pissing on unless you have a good half-dozen of them at a time.

(Oh, and your Alpha remark is indubitably true.)

 

[Tannin]

Tea, your proofreading is appalling.

 

[Clocker]

Saw this at AxionTech just incase SOI hasen't really been defined. It appears that SOI is a manufacturing process:

AMD Barton will not use SOI
by: Steven H. Liu


More Cache, No SOI
More Cache, No SOI


A recently disclosed AMD processor roadmap suggests that the company's 0.13µ SOI (Silicon-On-Insulator) manufacturing process, originally expected to debut in H2 2002 with the Barton, has indeed been pushed back to the end of 2002 or the beginning of 2003 with the Clawhammer.

However, rumors of the Barton core's cancellation due to the SOI process delay proved to be false. The newly disclosed roadmap suggests that AMD will instead introduce the Barton core in H2 2002 without the SOI. The core revision will retain its planned 512KB cache.

 

[James]

If the same amount of resources was poured into Alpha in the last decade as was poured into x86, I think Moore would have to admit he was overly pessimistic.

Who can forget the immortal words of Brannon Batson in comp.arch :

> BTW are you talking RISC or Intel here?
All you guys look the same in my rear-view mirror.

 

[timwhit]

Does SOI make the chip run faster? Or does it just allow for higher clock speeds in a given design?

Sorry for the elementary question, I haven't been paying attention in class lately.

 

[Tannin]

Less parasitic capacitance, mostly, if I remember correctly, which means fewer wasted electrons heating the thing up and thus faster clockspeeds. But Coug and HellDiver are both far better informed about this stuff that I am.

 

[HellDiver]

timwhit :

Basically, as Tony said. The "25 words or less" answer is that SOI allows to obtain higher clock frequencies and/or lower power dissipation for a given chip design.

If you're familiar with some electronics basics (e.g. know what transistor is) you may want to have a look at this IBM whitepaper on SOI - it outlines the basic principles behind SOI and mentiones a number of benefits of the technology as well as some implementation-related problems. Not too technical, so IMHO it's worth a look if you want to know more.

 

[timwhit]

I read the white paper. At least the part on SOI, the rest was fairly basic.

So if I am understanding this right. By implementing SOI in a chip, it should make the chip run faster at any given frequency since gates are opened and closed faster than before. Am I correct here?

So when is Intel going to move to SOI?

 

[HellDiver]

So if I am understanding this right. By implementing SOI in a chip, it should make the chip run faster at any given frequency since gates are opened and closed faster than before. Am I correct here?

Hmm... I though the WP would handle that...

No, you got it slightly wrong. First of all it's you don't "implement SOI in a chip", but rather you implement the chip on a SOI wafer. E.g. Soitec is a French wafer maker that specializes in SOI (hence the name), AMD placed a fairly big contract with them for wafers to make Hammers on.

And no, SOI will not "make the chip run faster at any given frequency". First, a little theory... Transistor is one of the atom building blocks of ICs. If you've read the WP you should have the basic understanding of how a transistor works. In overwhelming majority of ICs today things happen synchronously : i.e. groups of transistors receive signals on one [or two of the three] of their leads at once. By orchestrating what transistors in a CPU receive what signals at what times you make your sets of transistors do some productive work for you - e.g. calculate 1+1. It takes a transistor certain time to switch between the two states it can be in (*). The longer it takes a transistor to change state, the less times per second it can change states (strightforward logic). Hz = 1/Sec. I.e. a transistor that can change state at a frequency of 1GHz can change its state from open to closed and vice versa up to 1 billion times a second.

Every logical block in a CPU (e.g. integer ALU, FPU, AGU) consists of hundreds of thousands (in today's CPUs - even millions) of transistors [and sometimes other atom units for a good measure] that receive clock signal at certain times. The faster those transistors can switch, the higher frequency clock signal you can supply to that specific CPU block. That's the only way to make a given CPU design faster - by rising the clock frequency to perform more atom operations per second. So, "gates are opened and closed faster" and "at any given frequency" in the same sentence is and oxymoron in this context.

I hope the above explanation is decypherable to a non-electronics savvy person. If not - ask away.

So when is Intel going to move to SOI?

That's a good question. Until very recently, Intel (along with many other companies in the business) claimed that they didn't plant to migrate their designs to SOI. Among the stated reasons were claims that SOI benefits are deminishing as designs keep shrinking (e.g. some claim that already at 0.065u manufacturing process those will be non-existent). However, fairly recently (Nov 2001) Intel announced some neat plans using DST (Depleted Substrate Transistors) technology and "TeraHertz" marketing term, and even more recently (this months) they made available a presentation on the subj. According to this document, DST is just another form of SOI - just with different [and more advanced] characteristics. IIRC Intel plans on using DST technology in Prescott core. I might be wrong on the last one, though...

---------------------------
(*) Actually a transistor can be in one of three states, not two, but digital electronics only put two of those states to good use - open and closed. In the third state, the current you apply to the Base controls "how open" your switch is, i.e. how much current will pass from one of the other two leads to another. This third state of transistors is widely used in analog electronics, e.g. amplifiers.

Glossary :
IC - Integrated Circuit.
ALU - Arithmetic-Logic Unit.
AGU - Address Generation Unit.
FPU - Floating Point Unit.

 

[Tea]

Thanks HD. A nice, readily understandable refresher course.

 

[Cliptin]

In other words, lets assume there is a chip that in a certain design will only clock (even overclock) to 300MHz even under radical cooling. Someone makes the exact same chip except with SOI. The SOI version will not perform any better than the non SOI version.

Performance improvement comes with a die shrink or chip redesign. This is why you would never see an SOI version of the same chip unless it was to produce a chip that was less power hungry.

Where it gets fuzzy for me is:
Either SOI makes a die shrink easier or the two can work in parellel. My bet is SOI helps retard electron migration.

 

[Buck]

Either SOI makes a die shrink easier or the two can work in parellel. My bet is SOI helps retard electron migration.

Not that I've contributed much to this thread, my guess is the same.

 

[Pradeep]

In other words, lets assume there is a chip that in a certain design will only clock (even overclock) to 300MHz even under radical cooling. Someone makes the exact same chip except with SOI. The SOI version will not perform any better than the non SOI version.

Yes, but with any luck the SOI version wil overclock higher.

 

[HellDiver]

In other words, lets assume there is a chip that in a certain design will only clock (even overclock) to 300MHz even under radical cooling. Someone makes the exact same chip except with SOI. The SOI version will not perform any better than the non SOI version.

From what I know from various whitepapers published to day - no, the SOI version will not perform any better than the non-SOI version as long as it runs at the same clock speed. But one of the benefits of SOI is that you should be able to run a given logical design at a faster clock speed.

There is one catch here AFAIK, however - I don't think you can take your existing process masks, project them on a SOI wafer and expect the result to work "out of the box", so to speak. Since your physical properties of the transistors changed, it is likely you will have to adjust the physical design slightly. A narrower/wider gate, a slightly deeper or shallower drain or source - my guess is as good as yours, I've never worked with such advanced dies. AFAIK the simulation tools of PSpice and higher-end should be able to calc the physics of the die and provide you the answers on what exactly should be adjusted to get the desired result (even if at cost of several hundreds of hours of simulations running on multi-CPU SMPs). But your logical chip design can remain pretty much without changes - i.e. same TLBs, same physical floorplan, etc.

Performance improvement comes with a die shrink or chip redesign.

At a given frequency - performance improvements come with chip logical redesign. A die shrink is nothing but a way to make a given logical design run at a higher clock frequency. Low-k dielectrics and SOI are other ways to accomplish that (well, and to reduce dissipated power).

This is why you would never see an SOI version of the same chip unless it was to produce a chip that was less power hungry.

IMHO you'd never want to make a SOI version of a die that is about to die (no pun intended) in a couple of months for a different reason - it's a lot of money thrown out for nothing. IIRC SOI waffers cost today about 4-6 times more than bulk silicon, and as I mentioned you probably have to introduce some subtle changes at physical level, which means re-validation of a core. Why invest the money in 2-3 months worths of production if you can somehow limp through your current core and then invest the money in 6-12 months of production on a next core?

If any of you folks can point me to sources claiming otherwise - feel free to post links.

 

[LiamC]

Saw this on Ace's BB (originally from hardtechs4U) - release specs for T'bred

1800+ 1533 1.60V 0.13 56.9W 90 2nd May
1900+ 1600 1.60V 0.13 58.6W 90 2nd May
2000+ 1667 1.60V 0.13 60.3W 90 2nd May
2100+ 1733 1.60V 0.13 62.1W 90 2nd May
2200+ 1800 1.65V 0.13 67.9W 85 2nd May

2200+ is doing the same thing that P!!! 1.13GHz did - higher Vcore and lower Tdie, and we know how well teh P!!! 1.13GHz did! It's going to be a long slow summer for AMD unfortunately - but the upside is that they may have decided to concentrate on Hammer instead (wise move)

 

[Pradeep]

Saw this on Ace's BB (originally from hardtechs4U) - release specs for T'bred

1800+ 1533 1.60V 0.13 56.9W 90 2nd May
1900+ 1600 1.60V 0.13 58.6W 90 2nd May
2000+ 1667 1.60V 0.13 60.3W 90 2nd May
2100+ 1733 1.60V 0.13 62.1W 90 2nd May
2200+ 1800 1.65V 0.13 67.9W 85 2nd May

2200+ is doing the same thing that P!!! 1.13GHz did - higher Vcore and lower Tdie, and we know how well teh P!!! 1.13GHz did! It's going to be a long slow summer for AMD unfortunately - but the upside is that they may have decided to concentrate on Hammer instead (wise move)

Yes but the 1.65V is lower than the current voltage of the AthlonXP 1.73 GHz, it's not a simple overclock like the ill fated p3 1.13 GHz.