No VIA for me (well at least not in the first pass).
VIA does use HT and V-Link in it's chipset implementation.
In traditional (VIA) chipsets, the north bridge (NB) connects to the south bridge (SB) via (ha ha) V-Link. Other makers use their own variant (SiS) or the PCI bus (AMD 760, ALi MAGiK1).
With teh Clawhammer, things change somewhat because there is no traditional NB - but there is an AGP device.
VIA is using HT to talk from the CPU to the AGP device and then V-Link to their SB. This would have saved them development costs.
In all other chipsets (AMD, ALi, SiS, NVIDIA), it's HT all the way. This means that you could potentially use whichever AGP Tunnel (NB) and whichever SB gave you the features and price points that you desired. VIA seem to have cut themselves out of this market.
Note: I don't guarantee that it possible with all combinations. Some motherboard makers found out about design quirks when they wanted to develop MP Athlon chipsets with VIA SB's.
AS for the VIA PCI issue, I have been somewhat active on the Tech-Report BB about this issue.
1. Bus Parking is an Intel extension to the PCI 2.1 spec.
2. The core issue is whether support for Bus Park is required. From discussions with other posters more familiar with the PCI 2.1 specs than I, it seems that it is optional.
3. If point 2 is true, then card manufacturers should check for support before implementing. This points the foul finger of fate at card manufacturers.
4. If point 2 is not true, then VIA cannot claim (full) PCI 2.1 compliance.
This discussion should get interesting now this has come to light...
