Core I9

[LunarMist]

Because that's all they put on the CPUs. You still can't seem to put together any sort of specific hypothetical use case where it's going to actually pose a noticeable limit to yourself though. Or even, how about some benchmarks showing where it's a real limit vs. the Intel CPUs with more lanes?

I just want to use M.2s and the fully populated PCIe slots at the same time. Then I would believe it.
I was hoping to have the laptop to learn more of Windows 10 first though.

 

[Stereodude]

I just want to use M.2s and the fully populated PCIe slots at the same time. Then I would believe it.
I was hoping to have the laptop to learn more of Windows 10 first though.

And we went over this already that there are actually 40 lanes to play with. 16 from the CPU and 24 from the chipset. Unless the motherboard manufacturer totally screwed up filling all the slots should pose no problem.

 

[LunarMist]

So would you buy one instead of the Core I9 ?

 

[Chewy509]

16 from the CPU and 24 from the chipset.

But what is the interconnect between the the CPU and the PCH? It may mean those 24 PICe lanes on the PCH may have to share ~4.0GBps to the CPU.... (assuming the link is a DMI3.0 based interconnect).

 

[LunarMist]

But what is the interconnect between the the CPU and the PCH? It may mean those 24 PICe lanes on the PCH may have to share ~4.0GBps to the CPU.... (assuming the link is a DMI3.0 based interconnect).

Yes it is the DMI 3.0. The NVMe M.2 SSD can take most of that.

 

[Stereodude]

But what is the interconnect between the the CPU and the PCH? It may mean those 24 PICe lanes on the PCH may have to share ~4.0GBps to the CPU.... (assuming the link is a DMI3.0 based interconnect).

Yes, but so what? In what scenario does that present an actual throughput problem to him that's going to be perceptible?

 

[Stereodude]

Yes it is the DMI 3.0. The NVMe M.2 SSD can take most of that.

And when does that happen in real world use? When running SSD benchmarks? What other data do you need your system to be moving around while you're transferring data at max speed from the NVMe drive?

 

[LunarMist]

Of course I would not run SSD benchmarks whilst the system is doing something else. :roll:

 

[Chewy509]

Yes, but so what? In what scenario does that present an actual throughput problem to him that's going to be perceptible?

For most desktop and workstations users and their workloads, probably not...

At work, the device acquisition (for digital forensics) software we are building (and associated hardware platform), it is noticeable when acquiring a single NVMe device to a spanned set of NVMe target devices... and I fully admit, this is a very niche instance... At the moment with desktop hardware we can only image a NVMe at ~2GBps (worst case) due the DMI limitations, despite the underlying NVMe's being able to read/write faster...

Just as an edit: The only time I think uses would notice it, would be in disk imaging... I can't think of any other scenario where it may matter (outside of big data computation and you're not using a desktop for that).

 

[LunarMist]

Shouldn't they be using a better chipset?

 

[Stereodude]

For most desktop and workstations users and their workloads, probably not...

At work, the device acquisition (for digital forensics) software we are building (and associated hardware platform), it is noticeable when acquiring a single NVMe device to a spanned set of NVMe target devices... and I fully admit, this is a very niche instance... At the moment with desktop hardware we can only image a NVMe at ~2GBps (worst case) due the DMI limitations, despite the underlying NVMe's being able to read/write faster...

Just as an edit: The only time I think uses would notice it, would be in disk imaging... I can't think of any other scenario where it may matter (outside of big data computation and you're not using a desktop for that).

It doesn't use a DMA like scheme directly in the chipset to move data around without going through the CPU (and the DMI bridge)?

 

[sdbardwick]

It doesn't use a DMA like scheme directly in the chipset to move data around without going through the CPU (and the DMI bridge)?

AFAICT, DMA still exists in that you don't need the CPU to direct memory transfers (like old school PIO), but since the only physical access to memory is through the CPU die's IMC, all data transfers outside of RAM/cache go through PCIe/DMI.

 

[Chewy509]

@LM, who are you replying to?

 

[Chewy509]

It doesn't use a DMA like scheme directly in the chipset to move data around without going through the CPU (and the DMI bridge)?

For most forensic imaging software, no. Disk/Device images are stored in a container image format (typically EWF/E01 or AFF4), which contain additional metadata like case information, hashes (MD5/SHA1 or SHA512) of all the data, and these images are compressed as well (to save space), etc... Imaging for forensic based purposes is rarely just a bit-for-bit copy...