MoSys develops new space-saving way to add ECC on 1T-SRAM.

[CougTek]

Hi,

I stumbled on that news today while looking for something else.

"Reducing the cell size basically allows us to add ECC for 'free' while still staying within the standard design rules [of 0.13-micron processes]," he told SBN. "We are improving the soft error rate by a couple of orders of magnitude, taking it from 1,000 FITs [failures in time per megabit at 200 MHz] to roughly 10 FITs without increasing the size of the memory area."

MoSys said the new 1T-SRAM-R will pack a megabit of memory with error correction in 2 mm2 using 0.13-micron process design rules, while a six-transistor SRAM with ECC will take 5.5 mm2 to achieve the same level of soft error protection.

In addition to protection against soft errors in the field, the 1T-SRAM-R cell also helps to avoid the use of laser-repair steps in manufacturing, which lowers production costs and increases fab yields, according to MoSys.

I like the low space requirements of 1T-SRAM and its typically low latency (comparable to average SRAM), but it's sad that they can't use it at high frequencies. 200MHz is pretty slow by today's standard. I guess it could still be used as a cache....for the new PowerPC processors ;-) It can't be slower than the DDR memory that serves as a L2 cache on Apple latest PowerMac (their L2 cache has a mere 4GBps B/W).

I supposed 1T-SRAM is mostly used in communication devices and other proprietary designs.