SiS645 chipset, are you tempted to turn to Intel again?

[CougTek]

IMHO = In My Humble Opinion

That must not be an abreviation you use frequently because you don't emit your opinion in an humble manner most of the time, if not always, although sometimes you should.

Besides, it's not just about the amount of cache, it's also about its implementation. PIIIs CuMines with 256kb of L2 were faster than PIIIs with 512kb of L2 - latency and B/W as you mentioned are of paramount importance.

Like you wrote, it's all in the implementation. The 512Kb cache of the early PIII was external, low b/W and high latency. Integrating the cache on die resolved the low B/W and high latency issue (for that time). I propose to increase the amount of cache AND the width of the bus. Performance wise, I don't see how it could be slower.

There's absolutely nothing in eDRAM as in itself that would facilitate higher access B/W than that of SRAM. NADA.

Yes, there's one thing : size. eDRAM takes less space than conventional SRAM. This leaves more space on the die for something else. This economy of space can be used for additional overhead like more complex bus interface unit for instance. In a way, it does facilitate higher bandwidth.

Intel won't be selling its Northwood processors a lot higher than their Willamette despite a x2 Cache increased.

Well, first of all - we're yet to see about that!

The Northwood 1.8GHz and 1.6GHz are on my price list since monday and the price are more or less the same. Want to see for yourself?

To utilize the B/W afforded by a dual channel PC266/PC333 (umm... About 4.2GB/s - 5.4GB/s) you'd have to either double the FSB freq to 532MHz (266MHz DDR) or to go QDR on 133MHz (essentially P4-style bus). That would drive mobo prices up significantly (prolly 6 layers at least, etc. Even the more expensive Intel are still at 100MHz QDR equivalent!) Going 128bit on an FSB of a 32bit CPU sounds very doubtful, not to mention the price increase in this case!

Surprising, I can buy a Microstar 645 Ultra using SiS645 chipset with a 100MHz quad-pumped FSB / 4 layers PCB, for ~75U$. I hardly call that expensive. You know what's better? It can even operates at 533MHz FSB (4x133MHz)! All this to show that higher FSB doesn't necessarily translate into higher prices.

If SiS' engineers found a way to develop a cheap and fast FSB for the P4 platform, tell me why they wouldn't be able to do the same for AMD?

NRG's graph seems to proove this (higher FSB = big boost).

I'll bet you're a McDonalds lover!

Key word in my sentence was seems. I hate arrogance. End this thread alone. Whatever's the result of our pointless debate, Barton's faith doesn't depend on it.

 

[Tea]

Hey! Settle down you two! Don't you know there is a lady present?

 

[time]

When egos collide.

 

[HellDiver]

IMHO = In My Humble Opinion - That must not be an abreviation you use frequently

Actually, Coug, in this very specific thread, IMHO was used 5 times by me, and just once by you! 4 out of those 5 were used in a post that provoked your edgy reaction. How's that for a reality check?

Key word in my sentence was seems. I hate arrogance. End this thread alone. Whatever's the result of our pointless debate, Barton's faith doesn't depend on it.

That graph is synthetic. "proves" or "seems to prove" matters not, because traditionally P4 has beaten the crap out of Athlons synthetics-wise (without "seems"), but when it came to real world performace, the results were by far less than stellar.

Look, I'm sorry that you didn't know that eDRAMs/1T-SRAMs are slow-clocked. It just so happened that I've been following them for over a year, and you haven't. And your wish alone is still not enough to make them suitable for L1/L2 chaches (L2 except see prev post). Sorry.

Just like you I'd like AMD to keep winning the price/performance race against Intel. But unlike you I keep my feet on the ground, and also make sure to follow some published roadmaps. AMD is facing an uphill battle, and the next year will be much tougher than the previous.

Wishful thinking is a nice thing, generally speaking, but it gets you nowhere, Coug. Nowhere!

 

[CougTek]

End this thread alone.

Scratch that.

When egos collide.

Sadly, it's always like that between HellDiver and me. I won't speculate on the causes because it would only provoke additional reaction from the other side.

[cheap shot]

Actually, Coug, in this very specific thread, IMHO was used 5 times by me, and just once by you! 4 out of those 5 were used in a post that provoked your edgy reaction. How's that for a reality check?

Better to write it once and think it rather than write it five times but not wanting to be humble even once.
[/cheap shot]

Now to pursue the technical discussion :

x2 cache increase from 256kb to 512kb is not quite the same as for instance from 1mb to 2mb. Lets not forget, those babies come at 6T per bit, plus all the interconnects. 1MB of L2 can easily cost you >50 millions of tansistors. P4 + 256kb L2 is only 42 millions. AthlonXP + 256kb L2 is only 37.5 millions. You double the die - your yields plumet.

Not exactly. While it's logic to think that transistor count increase linearly the die size, it's not true. SRAM is more dense than logic circuitry and therefore takes less space. Take a look at the core pictures below :

You know where the cache is. The two large rectangles on the right side of the core and also the smaller one at the upper left corner. While it's obvious that the cache on the Northwood's die is proportionally bigger than the one on Willamette's die, it isn't twice as large physically despite being twice as large electronically.

Now take a look at McKinley's die :

It might not be obvious, but there's 3MB of cache on this die. I don't have the transistor count of McKinley's core, but I suspect that the 3MB of cache are probably 2/3 of the total transistors. As you can see however, the cache doesn't take 2/3 of the space on the die (it takes about 1/2). Why? Because cache is denser than the other parts of the die. (P.S. I don't find the damn transistor count for McKinley but I'm sure it's been published somewhere. If you find it - in your quest to proove me wrong - please post it)

When I wrote that an Athlon with a 1MB L2 cache would probably still be cheaper to produce than a Northwood CPU, it's because even with 1MB of cache, it's core would still be physically smaller, despite having a higher transistor count. Yield is a factor not to forget in the overall cost of a CPU and the x4 cache increase would certainly lower the current yield for the Palomino core. But another important factor is the number of cores per wafer. With a smaller die, the Athlon w/1MB cache would still be cheaper than Northwood because AMD would produce more CPUs per wafer than Intel. The yields would be horrible at the beginning (just like they were for Intel when they started to produce Willamette), but eventually, AMD would manage to find a way to increase it (like Intel did with Willamette).

Another BIG advantage AMD has (had?) is that they are using 300mm wafers compared to Intel's 200mm wafers. Intel is supposed to shift to 300mm wafers soon, but I don't think they have already. I'm not 100% sure about this though (that they are still stuck with 200mm wafers). Bigger wafers = more CPU per wafers = lower production cost per CPU.

 

[CougTek]

Hey! What hapened to my picture?

(Taking a look at TH's guide)

They removed it! See for yourself : http://www6.tomshardware.com/cpu/02q1/020107/p42200-04.html

Now a good part of my previous post goes down the drain

I guess it closes the discussion.

 

[CougTek]

Now the picture is back to normal, go figure.

 

[CougTek]

Intel is supposed to shift to 300mm wafers soon, but I don't think they have already.

Found the answer. Intel is going to start using 300mm wafers this quarter.

 

[HellDiver]

End this thread alone.

Scratch that.

No, actually I'm growing quite tired of this discussion, because I fail to see your point. I'm confused: are you trying to convince me that AMD will do A, B and C? Or that they should do A, B and C? Or that you thought that A was a good idea until you learned that there's a problem with it, but you still want them to do B and C?

I have a certain opinion regarding future AMD CPUs, which I presented here. You may sing praises to some technologies or try and prove me why doing other improvements is an excellent and cheap to implement idea. But this does not change my opinion on the subject. And right from here I will tell you that you won't see 1MB-cache desktop CPUs from AMD anytime soon, regardless of how cheap and easy it is in your opinion. Period. You think I say that because I'm arrogant. I think I say that because I've been in this shit for too long - starting from hardware design and ICs, through computer systems design and all the way into software design.

P.S. I don't find the damn transistor count for McKinley but I'm sure it's been published somewhere. If you find it - in your quest to proove me wrong - please post it

Grow up, Coug. If my opinion is different than yours and I happen to believe that your perception of certain technological aspects is wrong that still doesn't mean that I want to prove anything to anybody, let alone make it my quest. Stop being so egocentric, mate!

Supposedly circa 220 millions for 3MB cache version, bringing it up to about 465mm^2 on 0.18u.

You could have just asked, you know...

 

[Pradeep]

I believe AMD are still using 200mm wafers.

RE: Toms hardware pic, you can't link to it directly. You are seeing it because it is in your browser cache.

 

[HellDiver]

Pradeep :

Yes, they are, and will continue to do so till about 2004-2005, long after Intel will have 2-4 300mm fabs.

I think Coug wanted to say "copper" or "SOI" (soon to be) not "300mm"...

 

[CougTek]

I got misleaded somewhere, probably when reading license agreement about SOI between IBM and AMD. The 300mm wafer plans of major chip manufacturers can be found there.

Athlon's production cost is still significantly lower than P4's. Old news about it.