There appear to be errors in that table, eg PCIe 3.0 achieves 8 GT/s, not 5 GT/s, and the number of lanes should be 16, not 8.
H77 and H75/B75 are limited to a single 3.0 slot (no switching), but you can still run it at x8 alongside the 2.0 slots at x4 + x1 + x1. I was under the impression that...