Static wear leveling has such greater benefits for longevity and the cost can be mitigated by the over-provisioned area I can't imagine why a design would do otherwise.
Thanks for the link, but it remains, how many devices actually implement static wear leveling? (The costs are slowed writes and a higher performance controller is needed to offset slower writes, not to mention a proven firmware implementation, something which we all know companies will do anything to save a few cents on the BOM). I certainly hope that most decent SSDs do implement static wear leveling making my concerns mute.
The introduction of the TRIM command makes HD forensics very difficult if not impossible. Even a quick format will tell TRIM that the whole drive should be erased.
Something that we are now seeing in digital forensics with NAND, if chip-off acquisitions, where the NAND is removed from system board and controller, and is read independently... (Most NAND have JTAG pins for debugging purposes).
What has been seen is that a lot of device will not erase pages on a TRIM issue, but just mark the page as unused in the FTL/FTT (Flash Translation Layer/Flash Translation Table). Similarly, even with a SECURE ERASE command, not all controllers actually erase/overwrite the NAND itself. (Some that use encryption simply update to a new 3DES/AES key and call it done, but for giggles the old 3DES/AES key has been found with the NAND that accompanies the controller as well, making secure erase on those devices next to useless, and others simple wipe the FTL/FTT).
So in regards to Forensics, not all is lost... (We currently have a project at work that is doing chip-off acquisition on an iPhone4 - FYI, the phone was run over by a car, but the NAND itself seems ok). The cost for chip-off acquisition isn't as high as one would expect. (Sub $1000 in hardware and software that will target about 60% of the NAND on the market, providing you are willing to do some DYI).
